Actually there is a higher and higher evolution in the field of the radio frequency devices used in communication appliances as, for example, amplifiers in output stages of cellular transmitters. The research of higher and higher performances of said radio frequency devices and of maximum compatibly thereof with the other components of the different radio frequency appliances, it has brought to the use of different technologies for forming these devices as the LDMOS technology.
The LDMOS semiconductor devices have better features than those of the MOS semiconductor devices at high frequency, that is between 500 Mhz and 2 Ghz, because they allow a better setting of the input signal and a diminution of the losses of part of the output power for mismatch.
However a correct design of the input structure and of all the layout of the semiconductor device is necessary to minimize further losses. The input structure is mainly constituted by the gate terminal of the LDMOS device.
In each elementary cell belonging to the LDMOS device the electric connection of the single gate terminals is obtained by means of a single contact point. Therefore, each gate terminal called commonly “gate finger”, may be constituted, for a concentrate parameter circuit, by a network RC wherein the resistor R is given by the resistor of the gate finger, formed generally in polysilicon, and the capacity C is essentially given by the capacity between the gate terminal and the source terminal of each single elementary cell. The propagation of a signal through the gate finger may therefore have a delay given by the value of the time constant RC.
Actually a technology for controlling the resistance of the gate finger consists of placing on the polysilicon of the gate finger a thin layer of high conductivity material as, for example, cobalt or tungsten silicide. Other technologies used provide LDMOS structures having two or three metallization levels in order to define more contact points without decreasing excessively the capacity component.
Normally the elementary cells belonging to a LDMOS device are placed in separated blocks and at a prefixed distance from each other. This is due to the fact that the arrangement and number thereof can increase the electromagnetic iteration thereof, thus causing a decreasing of the output power. This phenomenon, known even as “Power Combining effect”, depends just on the distance between the blocks and on the number of the blocks.